The present invention generally relates to integrated circuits, and particularly relates to chip scale packaging of flip chip integrated circuits.
Packaging technology represents an enabling element in the ongoing microelectronics revolution. As integrated circuits have shrunk, so too have the physical packages carrying these devices. Various techniques are used to minimize the physical space required for integrated circuits, and to accommodate the increasingly high number of signal connections associated with dense integrated circuit devices.
Common approaches include various chip-on-glass and chip-on-board technologies. In these, an integrated circuit die is mounted directly on a primary circuit substrate, covered only by a minimal amount of epoxy or resin. While offering certain advantages in high-volume manufacturing environments, integrated circuit devices of this nature place significant challenges on handling and testing.
Other approaches strike a balance between physical size and the practical considerations of handling and testing. So-called xe2x80x9cchip scale packagesxe2x80x9d (CSPs) attempt to provide physical packaging for integrated circuit die without increasing the total physical size substantially beyond that of the actual die. Ideally, such packages remain as small as possible while still providing relatively robust protection for the die itself.
Chip scale packaging techniques may incorporate flip chip technology. With flip chip technology, an integrated circuit die having connections on its top-side is literally flipped over and mounted upside down to provide more direct interconnection to various circuit elements within the die. In a CSP incorporating flip chip technology, an integrated circuit die is flipped over and mounted top-side down to a chip carrier.
The chip carrier functions much like a printed circuit board, providing a rigid platform that can be readily handled and easily mounted to a larger circuit board carrying other electrical or electronic circuits. Essentially, the chip carrier provides practical access to the electrical interconnections of the flip chip it carries.
Typically, the chip carrier comprises a substrate having a top layer providing a number of conductive pads matched to the electrical connections of the flip chip. The flip chip is physically and electrically bonded to this top layer. Signal traces from the top layer pads are typically routed down through the substrate to its bottom layer. The bottom layer provides a set of conductive pads corresponding to the signal connections of the flip chip mounted to the top-side of the substrate. Oftentimes, the bottom layer pads have an expanded spacing or xe2x80x9cpitchxe2x80x9d as compared to the top layer connections to facilitate design and manufacturing processes. Commonly, the bottom layer pads carry solder balls or the like, that allow the CSP to be soldered to a primary circuit board using any suitable technique, such as reflow soldering.
While CSPs incorporating flip chip technology provide opportunities for managing high I/O count devices while still maintaining a small overall size, they are not without potential disadvantages. For example, while the flip chip interconnection with the integrated circuit die helps minimize connection impedance, the overall connection impedance between signal points on the die and a primary circuit board on which the CSP is mounted may still be excessive. The small size of the CSP may also be a disadvantage in terms of its thermal performance. The relatively high thermal impedance of conventional CSPs can be particularly problematic in high-performance devices.
The present invention provides a chip scale package adapted to carry a flip chip integrated circuit die, and incorporates certain features enhancing the electrical and thermal performance of the package. A flip chip integrated circuit die mounts to a corresponding set of connection pads on the top layer of a chip carrier. The top layer pads are arranged such that the signal and ground interconnections between the chip carrier and a flip chip itself are interleaved. This interleaving creates a signal-ground-signal transmission line structure adapted to carry high-frequency signals with minimal loss and interference. The alternating signal and ground connections are routed down from the top layer to a bottom layer of the chip carrier where they are terminated in solder ball connections suitable for mounting the chip carrier to a primary circuit board. Preserving the signal and ground interleaving on all signal layers of the chip carrier minimizes cross-signal coupling and signal path impedances.
The bottom layer of the chip carrier further comprises a centralized ground plane that includes a number of so-called xe2x80x9cthermalxe2x80x9d vias terminating in the top layer of the chip carrier. These thermal vias provide interconnection paths between the top layer and the bottom layer ground plane with low electrical and thermal impedances. The low thermal impedance of the thermal vias allows heat energy to flow from the flip chip device into the bottom layer ground plane. The bottom layer ground plane further comprises a number of solder balls for physically and electrically connecting the ground plane to the primary circuit board. These solder balls directly connect the ground plane to the primary circuit and thus complete the low electrical and thermal impedance paths from the top side of the carrier.